In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Persistent programming languages manage volatile memory as a cache for stable storage, imposing a read barrier on operations that access the cache, and a write barrier on updates ...
Antony L. Hosking, Nathaniel Nystrom, Quintin I. C...
In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identif...
As the speed gap between CPU and I/O is getting wider and wider, I/O latency plays a more important role to the overall system performance than it used to be. Prefetching consecut...
Tsozen Yeh, Joseph Arul, Kuo-Hsin Tien, I-Fan Chen...
Abstract— We consider the synchronization problem of an arbitrary number of coupled nonlinear oscillators with delays in the interconnections. The emphasis is on coupled Lorenz s...