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DATE
1999
IEEE
147views Hardware» more  DATE 1999»
14 years 1 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
POS
1998
Springer
14 years 1 months ago
Optimizing the Read and Write Barriers for Orthogonal Persistence
Persistent programming languages manage volatile memory as a cache for stable storage, imposing a read barrier on operations that access the cache, and a write barrier on updates ...
Antony L. Hosking, Nathaniel Nystrom, Quintin I. C...
DAC
2004
ACM
14 years 1 months ago
Implicit pseudo boolean enumeration algorithms for input vector control
In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identif...
Kaviraj Chopra, Sarma B. K. Vrudhula
CDES
2006
118views Hardware» more  CDES 2006»
13 years 11 months ago
Improving the System Performance by a Dynamic File Prediction Model
As the speed gap between CPU and I/O is getting wider and wider, I/O latency plays a more important role to the overall system performance than it used to be. Prefetching consecut...
Tsozen Yeh, Joseph Arul, Kuo-Hsin Tien, I-Fan Chen...
CDC
2008
IEEE
162views Control Systems» more  CDC 2008»
14 years 4 months ago
Synchronization in networks of nonlinear oscillators with coupling delays
Abstract— We consider the synchronization problem of an arbitrary number of coupled nonlinear oscillators with delays in the interconnections. The emphasis is on coupled Lorenz s...
Wim Michiels, Henk Nijmeijer