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VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
14 years 7 months ago
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos
IFM
2009
Springer
124views Formal Methods» more  IFM 2009»
14 years 2 months ago
Dynamic Path Reduction for Software Model Checking
We present the new technique of dynamic path reduction (DPR), which allows one to prune redundant paths from the state space of a program under verification. DPR is a very general...
Zijiang Yang, Bashar Al-Rawi, Karem Sakallah, Xiao...
DATE
2010
IEEE
153views Hardware» more  DATE 2010»
14 years 15 days ago
HORUS - high-dimensional Model Order Reduction via low moment-matching upgraded sampling
— This paper describes a Model Order Reduction algorithm for multi-dimensional parameterized systems, based on a sampling procedure which incorporates a low order moment matching...
Jorge Fernandez Villena, Luis Miguel Silveira
TCAD
2008
55views more  TCAD 2008»
13 years 7 months ago
Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process
Abstract--This paper presents a multiparameter momentmatching-based model order reduction technique for parameterized interconnect networks via a novel two-directional Arnoldi proc...
Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng
CDC
2009
IEEE
185views Control Systems» more  CDC 2009»
14 years 4 days ago
Discrete Empirical Interpolation for nonlinear model reduction
A dimension reduction method called Discrete Empirical Interpolation (DEIM) is proposed and shown to dramatically reduce the computational complexity of the popular Proper Orthogo...
Saifon Chaturantabut, Danny C. Sorensen