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126
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ISVLSI
2005
IEEE
129views VLSI» more  ISVLSI 2005»
15 years 8 months ago
Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki...
97
Voted
CONCUR
2005
Springer
15 years 8 months ago
Deriving Weak Bisimulation Congruences from Reduction Systems
The focus of process calculi is interaction rather than computation, and for this very reason: (i) their operational semantics is conveniently expressed by labelled transition syst...
Roberto Bruni, Fabio Gadducci, Ugo Montanari, Pawe...
PATMOS
2004
Springer
15 years 8 months ago
Sleepy Stack Reduction of Leakage Power
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as...
Jun-Cheol Park, Vincent John Mooney III, Philipp P...
ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
15 years 7 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
147
Voted
DEON
2006
Springer
15 years 6 months ago
Strategic Deontic Temporal Logic as a Reduction to ATL, with an Application to Chisholm's Scenario
In this paper we extend earlier work on deontic deadlines in CTL to the framework of alternating time temporal logic (ATL). The resulting setting enables us to model several concep...
Jan Broersen