198 search results - page 27 / 40 » Supporting Cache Coherence in Heterogeneous Multiprocessor S... |
TC
2008
13 years 7 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
We propose methods for reducing the energy consumed by snoop requests in snoopy bus-based symmetric multiprocessor (SMP) systems. Observing that a large fraction of snoops do not ...
IPPS
2000
IEEE
14 years 1 days ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents the design and full prototype implementation of a configurable multiprocessor platform that supports distributed execution of applications described in UML 2.0...
IEEEPACT
2003
IEEE
14 years 28 days ago
2003
IEEE
This paper presents a framework for analyzing the performance of multithreaded programs using a model called a constraint graph. We review previous constraint graph definitions fo...