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ISCA
2005
IEEE
144views Hardware» more  ISCA 2005»
14 years 1 months ago
Scalable Load and Store Processing in Latency Tolerant Processors
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth...
VEE
2012
ACM
187views Virtualization» more  VEE 2012»
12 years 3 months ago
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support
Dynamic Binary Translators (DBT) and Dynamic Binary Optimization (DBO) by software are used widely for several reasons including performance, design simplification and virtualiza...
Demos Pavlou, Enric Gibert, Fernando Latorre, Anto...
MSS
1999
IEEE
115views Hardware» more  MSS 1999»
13 years 11 months ago
Managing Databases with Binary Large Objects
We present recommendations on Performance Management for databases supporting Binary Large Objects (BLOB) that, under a wide range of conditions, save both storage space and datab...
Michael Shapiro, Ethan L. Miller
ISCA
2012
IEEE
232views Hardware» more  ISCA 2012»
11 years 10 months ago
RADISH: Always-on sound and complete race detection in software and hardware
Data-race freedom is a valuable safety property for multithreaded programs that helps with catching bugs, simplifying memory consistency model semantics, and verifying and enforci...
Joseph Devietti, Benjamin P. Wood, Karin Strauss, ...
HPCA
2007
IEEE
14 years 7 months ago
HARD: Hardware-Assisted Lockset-based Race Detection
The emergence of multicore architectures will lead to an increase in the use of multithreaded applications that are prone to synchronization bugs, such as data races. Software sol...
Pin Zhou, Radu Teodorescu, Yuanyuan Zhou