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» Supporting SELL for High-Performance Computing
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TPDS
2002
105views more  TPDS 2002»
13 years 7 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
WAIM
2007
Springer
14 years 1 months ago
A New DBMS Architecture for DB-IR Integration
Nowadays, as there is an increasing need to integrate the DBMS (for structured data) with Information Retrieval (IR) features (for unstructured data), DB-IR integration becomes one...
Kyu-Young Whang
LCN
2003
IEEE
14 years 24 days ago
Improving the Aggregate Throughput of Access Points in IEEE 802.11 Wireless LANs
In IEEE 802.11 wireless LANs, the DCF access method and the PCF access method operate alternatively within a superframe to service the time-varying traffic demands. Due to differ...
X. James Dong, Mustafa Ergen, Pravin Varaiya, Anuj...
DAC
2001
ACM
14 years 8 months ago
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems
Power-aware systems are those that must make the best use of available power. They subsume traditional low-power systems in that they must not only minimize power when the budget ...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi ...
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 8 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...