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IEEEPACT
2005
IEEE
14 years 2 months ago
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
Huiyang Zhou
ICS
2001
Tsinghua U.
14 years 1 months ago
Slice-processors: an implementation of operation-based prediction
We describe the Slice Processor micro-architecture that implements a generalized operation-based prefetching mechanism. Operation-based prefetchers predict the series of operation...
Andreas Moshovos, Dionisios N. Pnevmatikatos, Amir...
ATAL
2006
Springer
14 years 9 days ago
Gradient field-based task assignment in an AGV transportation system
Assigning tasks to agents is complex, especially in highly dynamic environments. Typical protocol-based approaches for task assignment such as Contract Net have proven their value...
Danny Weyns, Nelis Boucké, Tom Holvoet
CONCURRENCY
2002
230views more  CONCURRENCY 2002»
13 years 8 months ago
Economic models for resource management and scheduling in Grid computing
: The accelerated development in Peer-to-Peer (P2P) and Grid computing has positioned them as promising next generation computing platforms. They enable the creation of Virtual Ent...
Rajkumar Buyya, David Abramson, Jonathan Giddy, He...
HPCA
2009
IEEE
14 years 9 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...