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ICCAD
2010
IEEE
140views Hardware» more  ICCAD 2010»
15 years 1 months ago
Reduction of interpolants for logic synthesis
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
John D. Backes, Marc D. Riedel
153
Voted
BIRTHDAY
1999
Springer
15 years 8 months ago
Compilation and Synthesis for Real-Time Embedded Controllers
Abstract. This article provides an overview over two constructive approaches to provably correct hard real-time code generation where hard real-time code is generated from abstract...
Martin Fränzle, Markus Müller-Olm
156
Voted
DAC
1997
ACM
15 years 8 months ago
System-Level Synthesis of Low-Power Hard Real-Time Systems
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
Darko Kirovski, Miodrag Potkonjak
111
Voted
ASPDAC
2005
ACM
80views Hardware» more  ASPDAC 2005»
15 years 5 months ago
Synthesis of quantum logic circuits
— The pressure of fundamental limits on classical computation and the promise of exponential speedups from quantum effects have recently brought quantum circuits to the attention...
Vivek V. Shende, Stephen S. Bullock, Igor L. Marko...
DAC
2009
ACM
16 years 4 months ago
BDD-based synthesis of reversible logic for large functions
Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-pow...
Robert Wille, Rolf Drechsler