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DATE
2009
IEEE
100views Hardware» more  DATE 2009»
14 years 2 months ago
Increasing the accuracy of SAT-based debugging
Equivalence checking and property checking are powerful techniques to detect error traces. Debugging these traces is a time consuming design task where automation provides help. I...
André Sülflow, Görschwin Fey, C&e...
TACAS
2005
Springer
115views Algorithms» more  TACAS 2005»
14 years 1 months ago
On-the-Fly Reachability and Cycle Detection for Recursive State Machines
Searching the state space of a system using enumerative and on-the-fly depth-first traversal is an established technique for model checking finite-state systems. In this paper, ...
Rajeev Alur, Swarat Chaudhuri, Kousha Etessami, P....
IBMRD
2006
63views more  IBMRD 2006»
13 years 7 months ago
Decomposing the load-store queue by function for power reduction and scalability
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...
Lee Baugh, Craig B. Zilles
ARSCOM
2002
53views more  ARSCOM 2002»
13 years 7 months ago
Embedding Graphs Containing K5-Subdivisions
Given a non-planar graph G with a subdivision of K5 as a subgraph, we can either transform the K5-subdivision into a K3,3-subdivision if it is possible, or else we obtain a partit...
Andrei V. Gagarin, William Kocay
FMICS
2006
Springer
13 years 11 months ago
SAT-Based Verification of LTL Formulas
Abstract. Bounded model checking (BMC) based on satisfiability testing (SAT) has been introduced as a complementary technique to BDDbased symbolic model checking of LTL properties ...
Wenhui Zhang