788 search results - page 9 / 158 » Symbolic Equivalence Checking |
ASPDAC
2009
ACM
14 years 1 months ago
2009
ACM
Iterative retiming and resynthesis is a powerful way to optimize sequential circuits but its massive adoption has been hampered by the hardness of verification. This paper tackle...
DAC
2007
ACM
14 years 21 days ago
2007
ACM
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
DAC
2009
ACM
14 years 1 months ago
2009
ACM
We present a novel technique for Sequential Equivalence Checking (SEC) between non-cycle-accurate designs. The problem is routinely encountered in verifying the correctness of a s...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
Previous results show that both flat and hierarchical methodologies present obstacles to effectively completing combinational equivalence checking. A new approach that combines th...
ICCAD
2007
IEEE
14 years 5 months ago
2007
IEEE
Retiming and resynthesis are among the most important techniques for practical sequential circuit optimization. However, their applicability is much limited due to verification c...