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DATE
2007
IEEE
145views Hardware» more  DATE 2007»
14 years 1 months ago
Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
Riccardo Mariani, Gabriele Boschi, Federico Colucc...
DFT
2007
IEEE
101views VLSI» more  DFT 2007»
14 years 1 months ago
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits
Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, vari...
Francesco Regazzoni, Thomas Eisenbarth, Johann Gro...
CF
2004
ACM
14 years 1 months ago
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
Fernanda Lima Kastensmidt, Gustavo Neuberger, Luig...
ISOLA
2004
Springer
14 years 29 days ago
Designing Safe, Reliable Systems using Scade
As safety critical systems increase in size and complexity, the need for efficient tools to verify their reliability grows. In this paper we present a tool that helps engineers des...
Parosh Aziz Abdulla, Johan Deneaux, Gunnar St&arin...
IEEEAMS
2003
IEEE
14 years 27 days ago
JAGR: An Autonomous Self-Recovering Application Server
This paper demonstrates that the dependability of generic, evolving J2EE applications can be enhanced through a combination of a few recovery-oriented techniques. Our goal is to r...
George Candea, Emre Kiciman, Steve Zhang, Pedram K...