321 search results - page 34 / 65 » Symbolic Model Checking for Probabilistic Timed Automata |
ICCD
1995
IEEE
13 years 11 months ago
1995
IEEE
Symbolic model checking is a successful technique for checking properties of large finite-state systems. This method has been used to verify a number of real-world hardware desig...
ATVA
2004
Springer
14 years 28 days ago
2004
Springer
Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata Akio Nakata, Tadaaki Tanimoto, Suguru Sasaki, Teruo Higashino Department of Information Networking, ...
ATVA
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. This paper argues that flatness appears as a central notion in the verification of counter automata. A counter automaton is called flat when its control graph can be ...
DFG
2004
Springer
13 years 11 months ago
2004
Springer
Programmable Logic Controllers (PLC) are widespread in the manufacturing and processing industries to realize sequential procedures and to avoid safety-critical states. For the spe...
MEMOCODE
2006
IEEE
14 years 1 months ago
2006
IEEE
Timed I/O Automata (TIOA) is a mathematical framework for modeling and verification of distributed systems that involve discrete and continuous dynamics. TIOA can be used for exa...