48 search results - page 7 / 10 » Symbolic functional and timing verification of transistor-le... |
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward w...
FMSD
2007
13 years 7 months ago
2007
Symbolic techniques based on Binary Decision Diagrams (BDDs) are widely employed for reasoning about temporal properties of hardware circuits and synchronous controllers. However, ...
FPL
2000
Springer
13 years 11 months ago
2000
Springer
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
GLVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
FPL
1999
Springer
13 years 11 months ago
1999
Springer
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...