96 search results - page 5 / 20 » Synapses as dynamic memory buffers |
ISCA
2012
IEEE
12 years 1 days ago
2012
IEEE
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
IWMM
2007
Springer
14 years 3 months ago
2007
Springer
We present and evaluate a new technique for detecting and eliminating memory leaks in programs with dynamic memory allocation. This technique observes the execution of the program...
ICPP
2003
IEEE
14 years 2 months ago
2003
IEEE
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
CASES
2007
ACM
14 years 1 months ago
2007
ACM
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
FTDCS
1999
IEEE
14 years 1 months ago
1999
IEEE
The impact of buffer management and priority scheduling is examined in stressful scenarios when the aggregate incoming traffic is higher than the output link capacity of an Asynch...