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» Synchronization of periodic clocks
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ISCAS
2006
IEEE
106views Hardware» more  ISCAS 2006»
16 years 3 days ago
A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time
—This paper presents a Frequency-Estimation Algorithm for the ADPLL designs instead of traditional binary frequency-search algorithm. With the proposed ADPLL architecture and syn...
Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu
ICCD
1992
IEEE
82views Hardware» more  ICCD 1992»
15 years 10 months ago
A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies
Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in ...
Erik Brunvand, Nick Michell, Kent F. Smith
153
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IPPS
2008
IEEE
16 years 14 days ago
Accurately measuring collective operations at massive scale
Accurate, reproducible and comparable measurement of collective operations is a complicated task. Although Different measurement schemes are implemented in wellknown benchmarks, m...
Torsten Hoefler, Timo Schneider, Andrew Lumsdaine
ICCD
1995
IEEE
51views Hardware» more  ICCD 1995»
15 years 9 months ago
Implementing a STARI chip
STARI is a high-speed signaling technique that uses both synchronous and self-timed circuits. To demonstrate STARI, a chip has been fabricated using the MOSIS 2 CMOS process. In a...
Mark R. Greenstreet
ACCESSNETS
2008
Springer
16 years 13 days ago
A Simulator of Periodically Switching Channels for Power Line Communications
An indoor power line is one of the most attractive media for in-home networks. However, there are many technical problems for achieving in-home power line communication (PLC) with ...
Taro Hayasaki, Daisuke Umehara, Satoshi Denno, Mas...