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DAC
1997
ACM
14 years 23 days ago
A C-Based RTL Design Verification Methodology for Complex Microprocessor
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon ...
CHES
2006
Springer
88views Cryptology» more  CHES 2006»
14 years 9 days ago
Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage
Recent research has shown that cryptographers with glitches are vulnerable in front of Side Channel Attacks (SCA). Since then, several methods, such as Wave Dynamic Differential Lo...
Zhimin Chen, Yujie Zhou
WSC
1998
13 years 10 months ago
SEAMS: Simulation Environment for VHDL-AMS
VHDL-AMS is an Analog and Mixed-Signal extension to the Very High Speed Integrated Circuit Hardware Description Language (VHDL). With the standardization of VHDL-AMS, capable and ...
Peter Frey, Kathiresan Nellayappan, Vasudevan Sahn...
CONCUR
2010
Springer
13 years 8 months ago
On the Compositionality of Round Abstraction
ompositionality of Round Abstraction Abstract Dan R. Ghica and Mohamed N. Menaa University of Birmingham, U.K. We revisit a technique called round abstraction as a solution to the ...
Dan R. Ghica, Mohamed N. Menaa
IJON
2006
189views more  IJON 2006»
13 years 8 months ago
Storing and restoring visual input with collaborative rank coding and associative memory
Associative memory in cortical circuits has been held as a major mechanism for content-addressable memory. Hebbian synapses implement associative memory efficiently when storing s...
Martin Rehn, Friedrich T. Sommer