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» Synthesis: Words and Traces
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CODES
2010
IEEE
13 years 5 months ago
Automatic memory partitioning: increasing memory parallelism via data structure partitioning
In high-level synthesis, pipelined designs are often restricted by the number of memory banks available to the synthesis system. Using multiple memory banks can improve the perfor...
Yosi Ben-Asher, Nadav Rotem
SIAMMA
2010
102views more  SIAMMA 2010»
13 years 3 months ago
Trace Theorems for a Class of Ramified Domains with Self-Similar Fractal Boundaries
This work deals with trace theorems for a class of ramified bidimensional domains with a self-similar fractal boundary . The fractal boundary is supplied with a probability measur...
Yves Achdou, Nicoletta Tchou
ENTCS
2007
130views more  ENTCS 2007»
13 years 8 months ago
Specify, Compile, Run: Hardware from PSL
We propose to use a formal specification language as a high-level hardware description language. Formal languages allow for compact, unambiguous representations and yield designs...
Roderick Bloem, Stefan Galler, Barbara Jobstmann, ...
AUTOMATICA
2004
147views more  AUTOMATICA 2004»
13 years 8 months ago
Interval analysis and dioid: application to robust controller design for timed event graphs
This paper deals with feedback controller synthesis for timed event graphs in dioids, where the number of initial tokens and time delays are only known to belong to intervals. We ...
Mehdi Lhommeau, Laurent Hardouin, Bertrand Cottenc...
ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
14 years 1 months ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá