In high-level synthesis, pipelined designs are often restricted by the number of memory banks available to the synthesis system. Using multiple memory banks can improve the perfor...
This work deals with trace theorems for a class of ramified bidimensional domains with a self-similar fractal boundary . The fractal boundary is supplied with a probability measur...
We propose to use a formal specification language as a high-level hardware description language. Formal languages allow for compact, unambiguous representations and yield designs...
Roderick Bloem, Stefan Galler, Barbara Jobstmann, ...
This paper deals with feedback controller synthesis for timed event graphs in dioids, where the number of initial tokens and time delays are only known to belong to intervals. We ...
Mehdi Lhommeau, Laurent Hardouin, Bertrand Cottenc...
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...