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» Synthesis of Asynchronous Hardware from Petri Nets
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CMG
2003
13 years 9 months ago
{Performance Modeling and Evaluation of Large-Scale J2EE Applications
The queueing Petri net (QPN) paradigm provides a number of benefits over conventional modeling paradigms such as queueing networks and generalized stochastic Petri nets. Using qu...
Samuel Kounev, Alejandro P. Buchmann
POPL
2009
ACM
14 years 8 months ago
Verifying liveness for asynchronous programs
Asynchronous or "event-driven" programming is a popular technique to efficiently and flexibly manage concurrent interactions. In these programs, the programmer can post ...
Pierre Ganty, Rupak Majumdar, Andrey Rybalchenko
ICCD
1992
IEEE
84views Hardware» more  ICCD 1992»
13 years 11 months ago
Synthesis of 3D Asynchronous State Machines
We describe a new synthesis procedure for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental m...
Kenneth Y. Yun, David L. Dill, Steven M. Nowick
ASYNC
2003
IEEE
119views Hardware» more  ASYNC 2003»
14 years 24 days ago
Asynchronous DRAM Design and Synthesis
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
Virantha N. Ekanayake, Rajit Manohar
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
13 years 11 months ago
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
Jordi Cortadella, Michael Kishinevsky, Steven M. B...