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JSAC
2006
100views more  JSAC 2006»
13 years 8 months ago
Backbone Topology Synthesis for Multiradio Mesh Networks
Wireless local area network (WLAN) systems are widely implemented today to provide hot-spot coverage. Operated typically in an infrastructure mode, each WLAN is managed by an acces...
Laura Huei-jiun Ju, Izhak Rubin
ACSD
2007
IEEE
103views Hardware» more  ACSD 2007»
14 years 2 months ago
Output-Determinacy and Asynchronous Circuit Synthesis
Signal Transition Graphs (STG) are a formalism for the description of asynchronous circuit behaviour. In this paper we propose (and justify) a formal semantics of nondeterministic...
Victor Khomenko, Mark Schäfer, Walter Vogler
SOFSEM
2012
Springer
12 years 4 months ago
Recent Challenges and Ideas in Temporal Synthesis
In automated synthesis, we transform a specification into a system that is guaranteed to satisfy the specification against all environments. While modelchecking theory has led to...
Orna Kupferman
PTS
2007
99views Hardware» more  PTS 2007»
13 years 10 months ago
Testing Input/Output Partial Order Automata
Abstract. We propose an extension of the Finite State Machine framework in distributed systems, using input/output partial order automata (IOPOA). In this model, transitions can be...
Stefan Haar, Claude Jard, Guy-Vincent Jourdan
ICCAD
1999
IEEE
125views Hardware» more  ICCAD 1999»
14 years 26 days ago
Direct synthesis of timed asynchronous circuits
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
Sung Tae Jung, Chris J. Myers