171 search results - page 6 / 35 » Synthesis of Efficient Linear Test Pattern Generators |
DAC
1997
ACM
14 years 1 months ago
1997
ACM
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...
ATS
2000
IEEE
14 years 1 months ago
2000
IEEE
We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are...
ATS
2009
IEEE
14 years 3 months ago
2009
IEEE
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
ICST
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper introduces a new method for generating test data that combines the benefits of equivalence partitioning, boundary value analysis and cause-effect analysis. It is suitab...
DAC
2000
ACM
14 years 10 months ago
2000
ACM
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...