Efficient built-in self-test algorithm for memory

We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are needed for the detection of coulping faults. As a result, the number of test patterns required is less than half of the traditional method, while the extra hardware is negligible.

• Type: Conference
• Year: 2000
• Where: ATS
• Authors: Sying-Jyan Wang, Chen-Jung Wei
• Keywords: ATS 2000, Built-in Self-test, Hardware, Pseudorandom Testing Algorithm, Test Patterns