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» Synthesis of Multimode digital signal processing systems
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2005
Springer
14 years 1 months ago
Reconfigurable Power-Aware Scalable Booth Multiplier
Abstract. An energy-efficient power-aware design is highly desirable for digital signal processing functions that encounter a wide diversity of operating scenarios in battery-power...
Hanho Lee
ICCAD
2000
IEEE
149views Hardware» more  ICCAD 2000»
14 years 3 days ago
Dynamic Response Time Optimization for SDF Graphs
Synchronous Data Flow (SDF) is a well-known model of computation that is widely used in the control engineering and digital signal processing domains. Existing scheduling methods ...
Dirk Ziegenbein, Jan Uerpmann, Ralph Ernst
CHI
1996
ACM
13 years 12 months ago
NewsComm: A Hand-Held Interface for Interactive Access to Structured Audio
The NewsComm system delivers personalized news and other program material as audio to mobile users through a hand-held playback device. This paper focuses on the iterative design ...
Deb K. Roy, Chris Schmandt
ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
13 years 11 months ago
A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications
- The use of reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such cores are being used for their flexibility, powerful functionality and low ...
Zhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan
ERSA
2009
147views Hardware» more  ERSA 2009»
13 years 5 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias