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WISES
2003
13 years 11 months ago
Intelligent UART Module for Real-Time Applications
— More and more fieldbus applications require a communication with real-time properties, while still being economically feasible. The fieldbuses LIN and TTP/A take this require...
Martin Delvai, Ulrike Eisenmann, Wilfried Elmenrei...
TCAD
2008
103views more  TCAD 2008»
13 years 9 months ago
Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
Rebecca L. Collins, Luca P. Carloni
ICS
2009
Tsinghua U.
14 years 4 months ago
High-performance CUDA kernel execution on FPGAs
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
Alexandros Papakonstantinou, Karthik Gururaj, John...
CODES
2006
IEEE
14 years 3 months ago
Generic netlist representation for system and PE level design exploration
Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems requir...
Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah,...
BMCBI
2006
117views more  BMCBI 2006»
13 years 9 months ago
Gene Designer: a synthetic biology tool for constructing artificial DNA segments
Background: Direct synthesis of genes is rapidly becoming the most efficient way to make functional genetic constructs and enables applications such as codon optimization, RNAi re...
Alan Villalobos, Jon E. Ness, Claes Gustafsson, Je...