419 search results - page 51 / 84 » Synthesis of networks on chips for 3D systems on chips |
HOTI
2008
IEEE
14 years 3 months ago
2008
IEEE
Much of high performance technical computing has moved from shared memory architectures to message based cluster systems. The development and wide adoption of the MPI parallel pro...
DGCI
2005
Springer
14 years 2 months ago
2005
Springer
Due to the restriction of SIMD mode to local operations in VLSI massively parallel vision chips, using programmable connections and asynchronous communications are key ingredients ...
CODES
2001
IEEE
14 years 9 days ago
2001
IEEE
The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the...
RSP
2005
IEEE
14 years 2 months ago
2005
IEEE
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
ICC
2007
IEEE
14 years 3 months ago
2007
IEEE
—The use of adaptively-routed wormhole switched k-ary n-cubes has been motivated by the high path diversity provided by the rich topology of this family of interconnection networ...