419 search results - page 59 / 84 » Synthesis of networks on chips for 3D systems on chips |
ISPD
2005
ACM
14 years 2 months ago
2005
ACM
This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an it...
DAC
2008
ACM
13 years 10 months ago
2008
ACM
Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation i...
JSAC
2006
13 years 8 months ago
2006
High-speed packet content inspection and filtering devices rely on a fast multi-pattern matching algorithm which is used to detect predefined keywords or signatures in the packets....
IJES
2008
13 years 8 months ago
2008
: On-chipimplementationofmultiprocessorsystemsneedstoplanarisetheinterconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor ...
ARC
2011
Springer
13 years 7 days ago
2011
Springer
Increasing transmission speeds in high-performance networks pose significant challenges to protecting the systems and networking infrastructure. Reconfigurable devices have alrea...