419 search results - page 64 / 84 » Synthesis of networks on chips for 3D systems on chips |
JCP
2008
13 years 8 months ago
2008
Abstract--In this paper, we report some results on hardware and software co-design of an adaptive linear neuron (ADALINE) based control system. A discrete-time Proportional-Integra...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper addresses the allocation of link capacities in the automated design process of a network-on-chip based system. Communication resource costs are minimized under Quality-...
LCTRTS
2005
Springer
14 years 2 months ago
2005
Springer
Debugging, testing, and profiling microcontroller programs are notoriously difficult. The lack of supporting software such as an operating system, a narrow interface to the hard...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
In this paper, a novel automatic approach for the concurrent topology and routing optimization that achieves a high quality network layout is proposed. This optimization is based ...
CODES
2009
IEEE
14 years 16 days ago
2009
IEEE
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a softwarelike ...