419 search results - page 66 / 84 » Synthesis of networks on chips for 3D systems on chips |
AHS
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
DAC
2003
ACM
14 years 9 months ago
2003
ACM
A low power wireless intercom system is designed and implemented. Two fully-operational ASICs, integrating custom and commercial IP, implement the entire digital portion of the pr...
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer s...
IWSOC
2005
IEEE
14 years 2 months ago
2005
IEEE
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
DATE
2003
IEEE
2003
IEEE
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
14 years 1 months ago
In this paper, we present an algorithm which automatically maps the IPs onto a generic regular Network on Chip (NoC) architecture and constructs a deadlock-free deterministic rout...