419 search results - page 68 / 84 » Synthesis of networks on chips for 3D systems on chips |
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP...
HIPEAC
2005
Springer
14 years 2 months ago
2005
Springer
Abstract. While cycle-accurate simulation tools have been widely used in modeling high-performance processors, such an approach can be hindered by the increasing complexity of the ...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
— Recurrent networks and hardware analogs that perform a winner-take-all computation have been studied extensively. This computation is rarely demonstrated in a spiking network o...
MDM
2009
Springer
14 years 3 months ago
2009
Springer
Continuous queries in Wireless Sensor Networks (WSNs) are founded on the premise of Query Routing Tree structures (denoted as T), which provide sensors with a path to the querying...
QEST
2007
IEEE
14 years 2 months ago
2007
IEEE
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...