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» Synthesis of networks on chips for 3D systems on chips
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CASES
2004
ACM
14 years 10 days ago
Automatic data partitioning for the agere payload plus network processor
With the ever-increasing pervasiveness of the Internet and its stringent performance requirements, network system designers have begun utilizing specialized chips to increase the ...
Steve Carr, Philip H. Sweany
CASES
2008
ACM
13 years 10 months ago
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 9 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
DSN
2004
IEEE
14 years 10 days ago
The Recursive NanoBox Processor Grid: A Reliable System Architecture for Unreliable Nanotechnology Devices
Advanced molecular nanotechnology devices are expected to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS de...
A. J. KleinOsowski, Kevin KleinOsowski, Vijay Rang...
NABIC
2010
13 years 3 months ago
Regional ACO-based routing for load-balancing in NoC systems
Abstract--Ant Colony Optimization (ACO) is a problemsolving technique that was inspired by the related research on the behavior of real-world ant colony. In the domain of Network-o...
Hsien-Kai Hsin, En-Jui Chang, Chih-Hao Chao, An-Ye...