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» System Design Validation Using Formal Models
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ICCAD
1994
IEEE
65views Hardware» more  ICCAD 1994»
14 years 9 days ago
Incremental formal design verification
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
Gitanjali Swamy, Robert K. Brayton
ISBMS
2010
Springer
14 years 1 months ago
A Theoretical Model for RF Ablation of Kidney Tissue and Its Experimental Validation
Radio-frequency (RF) ablation is a minimal invasive thermal therapy, currently considered as an alternative to surgery to eradicate small solid kidney tumors. Our aim is to underst...
Mihaela Pop, Sean R. H. Davidson, Mark Gertner, Mi...
SIGSOFT
2007
ACM
14 years 9 months ago
Symbolic message sequence charts
Message Sequence Charts (MSCs) are a widely used visual formalism for scenario-based specifications of distributed reactive systems. In its conventional usage, an MSC captures an ...
Abhik Roychoudhury, Ankit Goel, Bikram Sengupta
JIPS
2010
107views more  JIPS 2010»
13 years 3 months ago
Incremental Model-based Test Suite Reduction with Formal Concept Analysis
Test scenarios can be derived based on some system models for requirements validation purposes. Model-based test suite reduction aims to provide a smaller set of test scenarios whi...
Pin Ng, Richard Y. K. Fung, Ray W. M. Kong
DATE
2003
IEEE
98views Hardware» more  DATE 2003»
14 years 1 months ago
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
System-on-chip (SoC) designs use bus protocols for high performance data transfer among the Intellectual Property (IP) cores. These protocols incorporate advanced features such as...
Abhik Roychoudhury, Tulika Mitra, S. R. Karri