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» System Design Validation Using Formal Models
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DATE
2007
IEEE
123views Hardware» more  DATE 2007»
14 years 2 months ago
Clock domain crossing fault model and coverage metric for validation of SoC design
Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensiv...
Yi Feng 0002, Zheng Zhou, Dong Tong, Xu Cheng
DT
2000
88views more  DT 2000»
13 years 7 months ago
Postsilicon Validation Methodology for Microprocessors
f abstraction as applicable to break the problem's complexity, and innovating better techniques to address complexity of new microarchitectural features. Validation techniques...
Hemant G. Rotithor
ICOST
2007
Springer
14 years 2 months ago
Characterizing Safety of Integrated Services in Home Network System
This paper formalizes three kinds of safety to be satisfied by networked appliances and services in the emerging home network system (HNS). The local safety is defined by safety ...
Ben Yan, Masahide Nakamura, Lydie du Bousquet, Ken...
DAC
1997
ACM
13 years 11 months ago
Formal Verification of FIRE: A Case Study
We present our experiences with the formal verification of an automotive chip used to control the safety features in a car. We used a BDD based model checker in our work. We descr...
Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl P...
TVLSI
2008
152views more  TVLSI 2008»
13 years 7 months ago
MMV: A Metamodeling Based Microprocessor Validation Environment
With increasing levels of integration of multiple processing cores and new features to support software functionality, recent generations of microprocessors face difficult validati...
Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Di...