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» System Design Validation Using Formal Models
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CAISE
2006
Springer
13 years 10 months ago
An attempt to combine UML and formal methods to model airport security
The EDEMOI project aims to model standards that regulate airport security. It involves the production of a UML model, to support the validation activity, and a formal model for ver...
Yves Ledru, Régine Laleau, Michel Lemoine, ...
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
13 years 11 months ago
Context-Aware Performance Analysis for Efficient Embedded System Design
Performance analysis has many advantages in theory compared to simulation for the validation of complex embedded systems, but is rarely used in practice. To make analysis more att...
Marek Jersak, Rafik Henia, Rolf Ernst
ICCS
2007
Springer
14 years 2 months ago
Validating Evolving Simulations in COERCE
We seek to increase user confidence in simulations as they are adapted to meet new requirements. Our approach includes formal representation of uncertainty, lightweight validation,...
Paul F. Reynolds Jr., Michael Spiegel, Xinyu Liu, ...
CMSB
2008
Springer
13 years 9 months ago
Formal Analysis of Abnormal Excitation in Cardiac Tissue
We present the Piecewise Linear Approximation Model of Ion Channel contribution (PLAMIC) to cardiac excitation. We use the PLAMIC model to conduct formal analysis of cardiac arrhyt...
Pei Ye, Radu Grosu, Scott A. Smolka, Emilia Entche...
MEMOCODE
2010
IEEE
13 years 5 months ago
LTSs for translation validation of (multi-clocked) SIGNAL specifications
Design of critical embedded systems demands for guarantees on the reliability of the implementation/compilation of a specification. In general, this guarantee takes either the form...
Julio C. Peralta, Thierry Gautier, Loïc Besna...