10159 search results - page 67 / 2032 » System Design Validation Using Formal Models |
SLIP
2005
ACM
14 years 1 months ago
2005
ACM
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
FORTE
2004
13 years 9 months ago
2004
In this paper, we present an approach for modeling an existing web application using communicating finite automata model based on the userdefined properties to be validated. We ela...
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
— With the success of formal verification techniques like equivalence checking and model checking for hardware designs, there has been growing interest in applying such techniqu...
FMICS
2007
Springer
14 years 2 months ago
2007
Springer
Using PVS (Prototype Verification System), we prove that an industry designed scheduler for a smartcard personalization machine is safe and optimal. This scheduler has previously ...
CODES
2001
IEEE
13 years 11 months ago
2001
IEEE
We present a new design environment, called System Canvas, targeted at DSP and telecommunication system designs. Our environment uses an easy-to-use block-diagram syntax to specif...