2435 search results - page 13 / 487 » System Exploration of SystemC Designs |
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—Today verification, testing and debugging of SystemC models can be applied at an early stage in the design process. To support these techniques gaining required information of ...
FPT
2005
IEEE
14 years 2 months ago
2005
IEEE
We describe a communication-centric design methodology with SystemC that allows for efficient FPGA prototype generation of transaction level models (TLM). Using a framework compr...
WORDS
2005
IEEE
14 years 2 months ago
2005
IEEE
Reliable program Worst-Case Execution Time (WCET) estimates are a key component when designing and verifying real-time systems. One way to derive such estimates is by static WCET ...
FM
2008
Springer
13 years 10 months ago
2008
Springer
TLM (Transaction-Level Modeling) was introduced to cope with the increasing complexity of Systems-on-Chip designs by raising the modeling level. Currently, TLM is primarily used fo...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
When designing heterogeneous MP-SoCs designers have to take into account various objectives such as power, die size, flexibility, performance or programmability. But to be able t...