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ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
14 years 5 months ago
Robust system level design with analog platforms
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
FPL
2004
Springer
83views Hardware» more  FPL 2004»
14 years 2 months ago
System-Level Modeling of Dynamically Reconfigurable Co-processors
Dynamically reconfigurable co-processors (DRCs) are interesting design alternatives when both flexibility and performance are concerns. However, it is difficult to study the perfor...
Yang Qu, Kari Tiensyrjä, Kostas Masselos
DAC
2007
ACM
14 years 10 months ago
Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design
This work is motivated by the strong demand of reliability enhancement over flash memory. Our objective is to improve the endurance of flash memory with limited overhead and witho...
Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo
DATE
2006
IEEE
135views Hardware» more  DATE 2006»
14 years 3 months ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
DATE
2005
IEEE
122views Hardware» more  DATE 2005»
14 years 2 months ago
Systematic Transaction Level Modeling of Embedded Systems with SystemC
This paper gives an overview of a transaction level modeling (TLM) design flow for straightforward embedded system design with SystemC. The goal is to systematically develop both...
Wolfgang Klingauf