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CODES
2005
IEEE
14 years 2 months ago
System-level design automation tools for digital microfluidic biochips
Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom de...
Krishnendu Chakrabarty, Fei Su
DFT
2008
IEEE
138views VLSI» more  DFT 2008»
14 years 3 months ago
Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When do smaller less reliable devices make sense?
It is widely recognized that device and interconnect fabrics at the nanoscale will be characterized by an increased susceptibility to transient faults. This appears to be intrinsi...
Andrey V. Zykov, Gustavo de Veciana
DDEP
2000
Springer
14 years 1 months ago
Context-Aware Digital Documents Described in a High-Level Petri Net-Based Hypermedia System
As mobile computing becomes widespread, so will the need for digital document delivery by hypertextual means. A further trend will be the provision of the ability for devices to de...
Jin-Cheon Na, Richard Furuta
EIT
2009
IEEE
14 years 3 months ago
System-level memory modeling for bus-based memory architecture exploration
—System-level design (SLD) provides a solution to the challenge of increasing design complexity and time-to-market pressure in modern embedded system designs. In this paper, we p...
Zhongbo Cao, Ramon Mercado, Diane T. Rover
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
13 years 7 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...