Sciweavers

452 search results - page 52 / 91
» System Level Hardware-Software Design Exploration with XCS
Sort
View
CODES
2007
IEEE
14 years 3 months ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...
DAC
2003
ACM
14 years 10 months ago
An IDF-based trace transformation method for communication refinement
In the Artemis project [13], design space exploration of embedded systems is provided by modeling application behavior and architectural performance constraints separately. Mappin...
Andy D. Pimentel, Cagkan Erbas
PC
2000
120views Management» more  PC 2000»
13 years 8 months ago
Real-time sonar beamforming on high-performance distributed computers
Rapid advancements in acoustical beamforming techniques for array signal processing are producing algorithms with increased levels of computational complexity. Concomitantly, auto...
Alan D. George, Jeff Markwell, Ryan Fogarty
CODES
2007
IEEE
14 years 3 months ago
HW/SW co-design for Esterel processing
We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The startin...
Sascha Gädtke, Claus Traulsen, Reinhard von H...
CODES
2007
IEEE
14 years 3 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling