12333 search results - page 89 / 2467 » System Level Modelling for Hardware Software Systems |
137
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CSE
2009
IEEE
15 years 9 months ago
2009
IEEE
—In this paper we present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data pl...
122
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ISORC
2005
IEEE
15 years 8 months ago
2005
IEEE
Heuristic algorithms have enjoyed increasing interests and success in the context of Utility Accrual (UA) scheduling. However, few analytical results, such as bounds on task-level...
115
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FPGA
2007
ACM
15 years 6 months ago
2007
ACM
Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is a...
123
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ICPP
2009
IEEE
15 years 9 months ago
2009
IEEE
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
ICCAD
2008
IEEE
15 years 11 months ago
2008
IEEE
—Hardware Intellectual Property (IP) cores have emerged as an integral part of modern System–on–Chip (SoC) designs. However, IP vendors are facing major challenges to protect...