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» System Level Tools for DSP in FPGAs
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LCTRTS
2009
Springer
14 years 2 months ago
Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring
The fine-grained parallelism inherent in FPGAs has encouraged their use in packet processing systems. Debugging and performance evaluation of such complex designs can be signifi...
Paul Edward McKechnie, Michaela Blott, Wim Vanderb...
FCCM
2008
IEEE
160views VLSI» more  FCCM 2008»
14 years 2 months ago
Facilitating Processor-Based DPR Systems for non-DPR Experts
Currently, only Xilinx Field Programmable Gate Arrays (FPGAs) support Dynamic Partial Reconfiguration (DPR). While there is currently some Computer Aided Design (CAD) tool support...
Edward Chen, William A. Gruver, Dorian Sabaz, Lesl...
FPGA
1995
ACM
142views FPGA» more  FPGA 1995»
13 years 11 months ago
The Design of RPM: An FPGA-based Multiprocessor Emulator
Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improveme...
Koray Öner, Luiz André Barroso, Sasan ...
IPPS
2007
IEEE
14 years 1 months ago
Distributed IDS using Reconfigurable Hardware
With the rapid growth of computer networks and network infrastructures and increased dependency on the internet to carry out day-to-day activities, it is imperative that the compo...
Ashok Kumar Tummala, Parimal Patel
FPGA
2007
ACM
124views FPGA» more  FPGA 2007»
13 years 11 months ago
Efficient hardware checkpointing: concepts, overhead analysis, and implementation
Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is a...
Dirk Koch, Christian Haubelt, Jürgen Teich