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» System level design, a VHDL based approach
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EVOW
2001
Springer
15 years 10 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
COMPSAC
2009
IEEE
15 years 10 months ago
Tool Support for Design Pattern Recognition at Model Level
Given the rapid rise of model-driven software development methodologies, it is highly desirable that tools be developed to support the use of design patterns in this context. This...
Hong Zhu, Ian Bayley, Lijun Shan, Richard Amphlett
JSAC
2011
108views more  JSAC 2011»
15 years 24 days ago
A Model-Based Approach to Cognitive Radio Design
Abstract—Cognitive radio is a promising technology for fulfilling the spectrum and service requirements of future wireless communication systems. Real experimentation is a key f...
Jorg Lotze, Suhaib A. Fahmy, Juanjo Noguera, Linda...
TACO
2008
130views more  TACO 2008»
15 years 5 months ago
Efficient hardware code generation for FPGAs
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
Zhi Guo, Walid A. Najjar, Betul Buyukkurt
GLVLSI
2003
IEEE
202views VLSI» more  GLVLSI 2003»
15 years 11 months ago
System level design of real time face recognition architecture based on composite PCA
Design and implementation of a fast parallel architecture based on an improved principal component analysis (PCA) method called Composite PCA suitable for real-time face recogniti...
Rajkiran Gottumukkal, Vijayan K. Asari