5744 search results - page 31 / 1149 » System level design, a VHDL based approach |
137
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ISSS
2002
IEEE
15 years 10 months ago
2002
IEEE
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
160
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VLSI
2007
Springer
16 years 4 hour ago
2007
Springer
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
180
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IWPC
2006
IEEE
15 years 12 months ago
2006
IEEE
One of the important activities in re-engineering process is detecting design flaws. Such design flaws prevent an efficient maintenance, and further development of a system. Th...
181
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LCTRTS
2010
Springer
16 years 22 days ago
2010
Springer
This paper extends the methodology of analytic real-time analysis of distributed embedded systems towards merging and extracting sub-streams based on event type information. For e...
133
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AOIS
2003
15 years 7 months ago
2003
This paper reports on the design, implementation, and evaluation of a market-based recommender system that suggests relevant documents to users. The key feature of the system is t...