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EUROMICRO
1998
IEEE
14 years 1 months ago
System Level Modelling for Hardware/Software Systems
Industry is facing a crisis in the design of complex hardware/software systems. Due to the increasing complexity, the gap between the generation of a product idea and the realisat...
Jeroen Voeten, P. H. A. van der Putten, Marc Geile...
CODES
2007
IEEE
14 years 3 months ago
Complex task activation schemes in system level performance analysis
The design and analysis of today’s complex real-time systems requires advanced methods. Due to ever growing functionality, hardware complexity and component interaction, applyin...
Wolfgang Haid, Lothar Thiele
DSD
2006
IEEE
110views Hardware» more  DSD 2006»
14 years 3 months ago
A Flexible, Syntax Independent Representation (SIR) for System Level Design Models
System Level Design (SLD) is widely seen as a solution for bridging the gap between chip complexity and design productivity of Systems on Chip (SoC). SLD relieves the designer fro...
Ines Viskic, Rainer Dömer
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
14 years 3 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
GD
2007
Springer
14 years 3 months ago
Visualizing Internet Evolution on the Autonomous Systems Level
We propose a visualization approach for large dynamic graph structures with high degree variation and low diameter. In particular, we reduce visual complexity by multiple modes of ...
Krists Boitmanis, Ulrik Brandes, Christian Pich