88 search results - page 8 / 18 » System-Level Modeling of Dynamically Reconfigurable Hardware... |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
DFT
2003
IEEE
14 years 23 days ago
2003
IEEE
In the last years, new requirements in terms of vehicle performance increased significantly the amount of on-board electronics, thus raising more concern about safety and fault to...
FCCM
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper we present a novel use of an FPGA as a computing element for streaming based application. We investigate the virtualized execution of dynamic reconfigurable tasks. We...
CC
2008
Springer
13 years 9 months ago
2008
Springer
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
FPL
2008
Springer
13 years 9 months ago
2008
Springer
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit the changing needs of a computation during run time. The increa...