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ISSRE
2008
IEEE
14 years 3 months ago
Using Fault Modeling in Safety Cases
For many safety-critical systems a safety case is built as part of the certification or acceptance process. The safety case assembles evidence to justify that the design and imple...
Robyn R. Lutz, Ann Patterson-Hine
ACSAC
2008
IEEE
14 years 3 months ago
Defending Against Attacks on Main Memory Persistence
Main memory contains transient information for all resident applications. However, if memory chip contents survives power-off, e.g., via freezing DRAM chips, sensitive data such a...
William Enck, Kevin R. B. Butler, Thomas Richardso...
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
14 years 3 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
CODES
2005
IEEE
14 years 2 months ago
System-level design automation tools for digital microfluidic biochips
Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom de...
Krishnendu Chakrabarty, Fei Su
RTCSA
2006
IEEE
14 years 3 months ago
Predictable Interrupt Scheduling with Low Overhead for Real-Time Kernels
In this paper we analyze the traditional model of interrupt management and its inability to incorporate the reliability and temporal predictability demanded by real-time systems. ...
Luis E. Leyva-del-Foyo, Pedro Mejía-Alvarez...