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ASYNC
2000
IEEE
86views Hardware» more  ASYNC 2000»
14 years 3 days ago
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
George S. Taylor, Simon W. Moore, Steve Wilcox, Pe...
SC
2009
ACM
14 years 10 days ago
A framework for core-level modeling and design of reconfigurable computing algorithms
Reconfigurable computing (RC) is rapidly becoming a vital technology for many applications, from high-performance computing to embedded systems. The inherent advantages of custom-...
Gongyu Wang, Greg Stitt, Herman Lam, Alan D. Georg...
CODES
2005
IEEE
14 years 1 months ago
The design of a smart imaging core for automotive and consumer applications: a case study
This paper describes the design of a low-cost, low-power smart imaging core that can be embedded in cameras. The core integrates an ARM 9 processor, a camera interface and two spe...
Wido Kruijtzer, Winfried Gehrke, Víctor Rey...
IROS
2006
IEEE
88views Robotics» more  IROS 2006»
14 years 1 months ago
Reliability-Based Design Optimization of Robotic System Dynamic Performance
In this investigation a robotic system’s dynamic performance is optimized for high reliability under uncertainty. The dynamic capability equations allow designers to predict the...
Alan P. Bowling, John E. Renaud, Jeremy T. Newkirk...
EMSOFT
2004
Springer
14 years 1 months ago
Scheduling within temporal partitions: response-time analysis and server design
As the bandwidth of CPUs and networks continues to grow, it becomes more attractive, for efficiency reasons, to share such resources among several applications with the minimum le...
Luís Almeida, Paulo Pedreiras