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    CODES
    2006
    IEEE
    149views Software Engineering» more  CODES 2006»
    Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies
    14 years 1 months ago
    Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies
    Download  www.cs.york.ac.uk
    Real-time multi-media applications are increasingly being mapped onto MPSoC (multi-processor system-on-chip) platforms containing hardware-software IPs (intellectual property) alo...
    Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nali...
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    DAC
    2009
    ACM
    135views Computer Architecture» more  DAC 2009»
    Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
    14 years 8 months ago
    Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
    Download  www12.informatik.uni-erlangen.de
    In this paper, a design method for automotive architectures is proposed. The two main technical contributions are (i) a novel hardware/software architecture encoding that unifies ...
    Jürgen Teich, Martin Lukasiewycz, Michael Gla...
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    SC
    2004
    ACM
    133views Applied Computing» more  SC 2004»
    A Performance and Scalability Analysis of the BlueGene/L Architecture
    14 years 1 months ago
    A Performance and Scalability Analysis of the BlueGene/L Architecture
    Download  wwwc3.lanl.gov
    This paper is structured as follows. Section 2 gives an architectural description of BlueGene/L. Section 3 analyzes the issue of “computational noise” – the effect that the o...
    Kei Davis, Adolfy Hoisie, Greg Johnson, Darren J. ...
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    ISLPED
    2007
    ACM
    123views Hardware» more  ISLPED 2007»
    Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules
    13 years 9 months ago
    Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules
    Download  www.cs.zju.edu.cn
    We address power minimization of earliest deadline first and ratemonotonic schedules by voltage and frequency scaling. We prove that the problems are NP-hard, and present (1+ ) f...
    Sushu Zhang, Karam S. Chatha, Goran Konjevod
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    ACSD
    2006
    IEEE
    102views Hardware» more  ACSD 2006»
    Models of Computation for Networks on Chip
    13 years 9 months ago
    Models of Computation for Networks on Chip
    Download  web.it.kth.se
    Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making...
    Axel Jantsch
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