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GLVLSI
2005
IEEE
104views VLSI» more  GLVLSI 2005»
14 years 2 months ago
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
Ajay Joshi, Jeffrey A. Davis
RSP
2003
IEEE
132views Control Systems» more  RSP 2003»
14 years 2 months ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
SAMOS
2004
Springer
14 years 2 months ago
MOUSE: A Shortcut from Matlab Source to SIMD DSP Assembly Code
Abstract. This article presents a novel design flow called MOUSE for the effective development of digital signal processing systems in terms of development time, performance and p...
Gordon Cichon, Gerhard Fettweis
LCTRTS
2007
Springer
14 years 3 months ago
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Y...
RTCSA
2000
IEEE
14 years 1 months ago
Scheduling optional computations in fault-tolerant real-time systems
This paper introduces an exact schedulability analysis for the optional computation model urider a specified failure hypothesis. From this analysis, we propose a solutionfor deter...
Pedro Mejía-Alvarez, Hakan Aydin, Daniel Mo...