The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
Previous cognitive modelling work has suggested that the decline of short-term memory (STM) capacity is the dominant factor of age-related decline on recall ability. We report the...
Richard Ll. Smith, Peter C. R. Lane, Fernand Gobet
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
Francesco Menichelli, Mauro Olivieri, Luca Benini,...
The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching...
William Fornaciari, Donatella Sciuto, Cristina Sil...
This paper examines capacity limits in mental animation of static diagrams of mechanical systems and interprets these limits within current theories of working memory. I review emp...