93 search results - page 7 / 19 » System-level memory modeling for bus-based memory architectu... |
ARCS
2009
Springer
14 years 3 months ago
2009
Springer
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
EMS
2008
IEEE
14 years 3 months ago
2008
IEEE
Previous cognitive modelling work has suggested that the decline of short-term memory (STM) capacity is the dominant factor of age-related decline on recall ability. We report the...
DATE
2004
IEEE
14 years 8 days ago
2004
IEEE
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
CODES
1999
IEEE
14 years 26 days ago
1999
IEEE
The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching...
DIAGRAMS
2000
Springer
14 years 27 days ago
2000
Springer
This paper examines capacity limits in mental animation of static diagrams of mechanical systems and interprets these limits within current theories of working memory. I review emp...