392 search results - page 30 / 79 » System-level power estimation and optimization |
ISLPED
1999
ACM
14 years 2 months ago
1999
ACM
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
DAGSTUHL
2006
13 years 11 months ago
2006
Long-term reliability of processors in embedded systems is experiencing growing attention since decreasing feature sizes and increasing power consumption have a negative influence...
CC
2002
Springer
13 years 9 months ago
2002
Springer
Global variable promotion, i.e. allocating unaliased globals to registers, can significantly reduce the number of memory operations. This results in reduced cache activity and less...
ICASSP
2011
IEEE
13 years 1 months ago
2011
IEEE
Training sequences for estimation of channel parameters have been well designed under the condition that the number of the unknown channel parameters is not greater than the numbe...
DATE
2005
IEEE
14 years 3 months ago
2005
IEEE
When applying Dynamic Power Management (DPM) technique to pervasively deployed embedded systems, the technique needs to be very efficient so that it is feasible to implement the t...