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» System-level power estimation and optimization
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DAC
2005
ACM
14 years 10 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer
CODES
2002
IEEE
14 years 2 months ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh
SIGGRAPH
1995
ACM
14 years 1 months ago
Optimally combining sampling techniques for Monte Carlo rendering
Monte Carlo integration is a powerful technique for the evaluation of difficult integrals. Applications in rendering include distribution ray tracing, Monte Carlo path tracing, a...
Eric Veach, Leonidas J. Guibas
BMCBI
2008
105views more  BMCBI 2008»
13 years 9 months ago
Using the longest significance run to estimate region-specific p-values in genetic association mapping studies
Background: Association testing is a powerful tool for identifying disease susceptibility genes underlying complex diseases. Technological advances have yielded a dramatic increas...
Ie-Bin Lian, Yi-Hsien Lin, Ying-Chao Lin, Hsin-Cho...
DATE
1999
IEEE
112views Hardware» more  DATE 1999»
14 years 2 months ago
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will...
Markus Bühler, Matthias Papesch, K. Kapp, Utz...